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ARM EN0-001 Exam - Cheat-Test.com

Free EN0-001 Sample Questions:

Q: 1
Using a lower optimization level when compiling will:
A. Produce faster code.
B. Produce smaller code.
C. Produce non standard-compliant code.
D. Produce code that might be easier to debug.
Answer: D

Q: 2
Which instruction would be used to return from a Reset exception?
A. MOVS PC, R14
B. MOVSPC, R13
C. Architecturally not defined
D. SUBS PC, R14, #4
Answer: C

Q: 3
In a Cortex-A9 MPCore cluster with four processors, which of the processors can be interrupted by a software-generated interrupt?
A. Any processor in the cluster
B. Only the processor raising the software-generated interrupt
C. Only processors outside the cluster
D. Any processor except the one raising the software-generated interrupt
Answer: A

Q: 4
To return from a Data Abort handler and re-execute the aborting instruction, what value should be loaded to the PC?
A. PC=LR
B. PC=LR44
C. PC=LR-4
D. PC=LR-8
Answer: D

Q: 5
Which of the following register values would cause an unaligned access when the instruction LDRH r0, [r1] is executed?
A. R0=0x100, R1 =0x1000
B. R0=0x100, R1=0x1002
C. R0=0x101, R1=0x1002
D. R0=0x101. R1=0x1003
Answer: D

Q: 6
Which ARMv7 instructions are recommended to implement a semaphore?
A. SWP, SWPB
B. TEQ, TST
C. STC, SBC
D. LDREX, STREX
Answer: D

Q: 7
Within the ARMv7 architecture, which one of the following features is unique to the ARMv7-A profile?
A. Cache support
B. Privileged execution
C. The ARM instruction set
D. Virtual memory support
Answer: D

Q: 8
When programming in C, how many bytes of stack are needed to pass parameters when calling the following function?
int foo( int arg_a, int arg_b, int arg_c )
A. 0
B. 4
C. 8
D. 12
Answer: A

Q: 9
The following pseudocode sequence shows a flag being set to indicate that new data is ready to be read by another thread:
data = 123;
ready = true;
Assuming that the reader threads may execute on any other core of a multicore system, which of the following is the most efficient memory barrier to place between the two writes to prevent them being observed in the opposite order?
A. DSBSY
B. DSBST
C. DMBSY
D. DMBST
Answer: D

Q: 10
On a processor supporting the Security Extensions, what sequence of operations is required to move from Non-secure User mode to Secure state?
A. This transition is not possible
B. Execution of an SMC instruction
C. Execution of an SMC instruction followed by an SVC instruction
D. Execution of an SVC instruction followed by an SMC instruction
Answer: D


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